Since its introduction as an industry standard in 1990, boundary scan (also known as JTAG, developed by the Joint Test Action Group) has enjoyed growing popularity for board level manufacturing test applications. JTAG has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and IC level access capabilities of JTAG, its use has expanded beyond traditional board test applications into product design and service.
JTAG, as defined by the IEEE Std.-1149.1 standard, is an integrated method for testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC) level. The inability to test highly complex and dense printed circuit boards using traditional in-circuit testers and bed of nail fixtures was already evident in the mid eighties. Due to physical space constraints and loss of physical access to fine pitch components and BGA devices, fixturing cost increased dramatically while fixture reliability decreased at the same time.
The JTAG test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes. It adds a boundary-scan cell that includes a multiplexer and latches to each pin on the device. Boundary-scan cells in a device can capture data from pin or core logic signals, or force data onto pins. Captured data is serially shifted out and externally compared to the expected results. Forced test data is serially shifted into the boundary-scan cells. All of this is controlled from a serial data path called the scan path or scan chain. By allowing direct access to nets, JTAG eliminates the need for a large number of test vectors, which are normally needed to properly initialize sequential logic. Tens or hundreds of vectors may do the job that had previously required thousands of vectors. Potential benefits realized from the use of JTAG are shorter test times, higher test coverage, increased diagnostic capability and lower capital equipment cost.
If a circuit contains more than one device that supports JTAG, they can be linked together to form a ‘JTAG Chain’. In a JTAG chain the data output from the first device becomes the data input to the second device; the control and clock signals are common to all devices in the chain. FIG. 1 provides a representation of a simple JTAG chain containing three devices.
In FIG. 1 (Prior Art) devices 101, 102 and 103 have boundary scan implemented, and are connected as shown. JTAG employs four test connections:
TCK (105)—the TCK or ‘test clock’ synchronizes the internal state machine operations.
TMS (104)—the TMS or ‘test mode state’ is sampled at the rising edge of TCK to determine the next state.
TDI (106)—the TDI or ‘test data in’ represents the data shifted into the device's test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.
TDO (107)—the TDO or ‘test data out’ represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state.
The current trend for reduced product size, such as portable phones and digital cameras, higher functional integration, faster clock rates, and shorter product life-cycles with dramatically faster time to market has created new technology trends. These trends include increased device complexity, fine pitch components, such as Surface-Mount Technology (SMT), Multi Chip Modules (MCM), Ball Grid Arrays (BGA), increased IC pin counts and smaller PCB traces. These technology advances, in turn create problems in PCB development:
Many boards include components that are assembled on both sides of the board. Most of the through-holes and traces are buried and inaccessible.
Loss of physical access to fine pitch components, such as SMTs and BGAs makes it difficult to probe the pins and distinguish between manufacturing and design problems.
Small-size products do not have test points, making it difficult or impossible to probe suspected nodes.
Many Complex Programmable Logic Devices and flash memory devices are not socketed and are soldered directly to the board.
JTAG technology is the only cost effective solution that can deal with the above problems. In recent years, the number of devices that include JTAG has grown dramatically. Almost every new microprocessor that is being introduced includes JTAG circuitry for testing and in-circuit emulation
As the acceptance of JTAG as the main technology for interconnect testing and in-system programming has increased, the various JTAG test tools have matured as well. The increased number of JTAG components and mature JTAG tools, as well as other factors result in the following benefits:
Easy to implement Design For Testability (DFT) rules.
Design analysis prior to PCB layout to improve testability.
Packaging problems are found prior to PCB layout.
Little need for test points.
No need for test fixtures.
More control over the test process.
Quick diagnosis (with high resolution) of interconnection problems without writing any functional test code.
JTAG emulation and source-level debugging.